1. Technical Field
The present disclosure relates generally to shallow trench isolation features for isolating semiconductor devices. In particular, the present disclosure relates to a structure and method of forming shallow trench isolation structures using diblock copolymer patterning.
2. Description of Related Art
Modern integrated circuit manufacturing processes generally include millions of semiconductor devices, such as field effect transistors (FETs), having very small feature sizes. For example, gate electrodes and interconnects may include less than 0.08 μm in critical dimensions. As feature sizes continue to decrease, the size of the resulting device, as well as the interconnect between semiconductor devices must also decreases. Fabrication of smaller semiconductor devices allows more semiconductor devices to be positioned on a single monolithic semiconductor substrate, thereby allowing relatively large circuit systems to be incorporated on a single, relatively small die area.
Isolation structures, such as, for example, shallow trench isolations (STI), are provided between active regions of semiconductor devices for electrically isolating the semiconductor devices from one another. STI have become the most common and important isolation technology for sub-quarter micron complimentary metal oxide semiconductor (CMOS) devices. A conventional STI process flow includes forming a barrier oxide layer of SiO2 over a semiconductor substrate. A nitride layer is then deposited over the barrier oxide layer. Next, a shallow trench area having apertures are formed in the nitride layer and the barrier layer for exposing a surface of the semiconductor substrate. An oxide deposition is then performed following the formation of the shallow trench area in the semiconductor substrate. The oxide deposition process forms a field oxide layer (trench oxide) that fills the shallow trench and the apertures. The oxide on the top surface of the nitride layer is then removed using a chemical-mechanical planerization (CMP) method. In some cases, the liner oxide layer is formed interposed between the trench oxide and the semiconductor substrate. Finally, the nitride layer is stripped from the barrier oxide layer with one or more suitable stripping agents.
Another conventional STI process flow includes pad oxide and chemical vapor deposition (CVD) silicon nitride (SiN) deposition, active area masking, nitride/oxide etching, silicon (Si) trench etching, liner oxidation, high density plasma (HDP) oxide filing, chemical mechanical polishing (CMP) polishing, and nitride and pad oxide removal.
However, as semiconductor device scales, HDP oxide becomes very difficult to fill into the ever narrower STI trench opening. Thus, during a STI trench fill process, HDP oxide deposition needs to be stopped periodically and intermediate etching steps are inserted to remove HDP oxide from the top surface of the trench so that HDP oxide may be filled into the lower part of the trench in the resumed HDP oxide deposition step. Often, multiple deposition-etch-deposition steps are required to complete the filling of the trench opening. Moreover, HDP process often damages the exposed substrate and reduces gate oxide thickness at the corner of STI trench opening causing problems with reliability, etc.
In addition, CMP uses abrasive and corrosive chemical slurry in conjunction with a polishing pad. The pad and substrate are pressed together by a dynamic polishing head and held in place by a plastic retaining ring. The dynamic polishing head is rotated at different polishing speed and pressure. This process, while it removes for making the substrate flat or planar, the CMP process may create uneven surface topology due to the non-uniform polishing speed and pressure.
Accordingly, a need exists for forming STI structures using alternative methods circumventing the limitations of HDP oxide deposition and CMP. The present disclosure provides a method of forming STI structures using diblock copolymer patterning.